1. Field
Example embodiments relate to semiconductor packages, stacked semiconductor packages, and methods of manufacturing the semiconductor packages and the stacked semiconductor packages. Also, example embodiments relate to semiconductor packages including semiconductor devices, stacked semiconductor packages including the semiconductor devices, and methods of manufacturing the semiconductor packages and the stacked semiconductor packages including the semiconductor devices.
2. Description of Related Art
Generally, various semiconductor processes are carried out on a semiconductor substrate to form a plurality of semiconductor devices. To mount the semiconductor device on a motherboard, a packaging process is performed on the semiconductor substrate. According to a conventional packaging process, the semiconductor substrate is cut along a scribe lane to divide the semiconductor substrate into a plurality of semiconductor chips including semiconductor devices. Each of the semiconductor chips is attached to a circuit substrate. A bonding pad of the semiconductor chip and the circuit substrate are electrically connected to each other using a conductive wire. A mold is formed on the circuit substrate to cover the semiconductor chip with the mold. Outer terminals such as solder balls are mounted to the circuit substrate.
However, since the conventional packaging process is separately carried out on each of the semiconductor chips, the conventional packaging process may have a low efficiency.
To overcome the above-mentioned problem, a wafer level packaging process has recently been proposed. In the wafer level packaging process, before cutting a semiconductor substrate, a packaging process is carried out on the whole semiconductor substrate. The packaged semiconductor substrate is then cut to form a plurality of semiconductor packages.
Examples of conventional wafer level packaging processes are disclosed in Japanese Patent Laid-Open Publication Nos. 2002-050738 A, 2004-288722 A, and 2004-228392 A, etc.
According to the method in Japanese Patent Laid-Open Publication No. 2002-050738 A, a hole is formed through a semiconductor chip. An insulation layer is formed on an inner face of the hole. Wafer level packages are then stacked using the insulation layer as an adhesive.
According to the method in Japanese Patent Laid-Open Publication No. 2004-288722 A, holes are formed through a semiconductor chip. The holes are then filled with plugs. A supporting member is attached to an upper face of the semiconductor chip. A lower portion of the semiconductor chip is partially removed to expose the plugs. The exposed plugs are connected to each other to stack wafer level packages.
According to the method in Japanese Patent Laid-Open Publication No. 2004-228392 A, a hole is formed through a semiconductor chip. An electrode is then plated on an inner face of the hole. A supporting member is attached on an upper face of the semiconductor chip using an adhesive. A lower portion of the semiconductor chip is partially removed to expose the electrode.
However, in the above-mentioned conventional methods, when the lower portion of the semiconductor chip is removed, a lower face of the semiconductor chip as well as the plug may be partially exposed. This may cause a short circuit between a semiconductor substrate of an upper package and a plug of a lower package.
To prevent the short circuit between the semiconductor substrate and the plug, an insulation layer including silicon or photoresist may be formed on a lower face of the semiconductor substrate. However, since the insulation layer may be formed at a temperature of no less than about 100° C., the supporting member for supporting the semiconductor substrate may be detached from the semiconductor substrate due to thermal decomposition of the supporting member before a sawing process.